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74ACT16543 16-Bit Registered Transceiver with 3-STATE Outputs
August 1999 Revised October 1999
74ACT16543 16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ACT16543 contains sixteen non-inverting transceivers containing two sets of D-type registers for temporary storage of data flowing in either direction. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow.
Features
s Independent registers for A and B buses s Separate controls for data flow in each direction s Back-to-back registers for storage Multiplexed real-time and stored data transfers s Separate control logic for each byte s Outputs source/sink 24 mA s TTL-compatible inputs
Ordering Code:
Order Number 74ACT16543SSC 74ACT16543MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OEABn OEBAn CEABn CEBAn LEABn LEBAn A0-A15 B0-B15 Descriptions A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs
FACTTM is a trademark of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS500301
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74ACT16543
Functional Description
The ACT16543 contains sixteen non-inverting transceivers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The following description applies to each byte. For data flow from A to B, for example, the A-toB Enable (CEABn) input must be LOW in order to enter data from A0-A15 or take data from B0-B15, as indicated in the Data I/O Control Table. With CEABn LOW, a LOW signal on the A-to-B Latch Enable (LEABn) input makes the Ato-B latches transparent; a subsequent LOW-to-HIGH transition of the LEABn signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEABn and OEABn both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBAn, LEBAn and OEBAn inputs.
Data I/O Control Table
Inputs CEABn H X L X L LEABn X H L X X OEABn X X X H L Latch Status (Byte n) Latched Latched Transparent -- -- Output Buffers (Byte n) High Z -- -- High Z Driving
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBA n and OEBAn
Logic Diagrams
Byte 1 (0:7) Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACT16543
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current per Output Pin Storage Temperature 50 mA -65C to +150C -20 mA +20 mA -0.5V to VCC + 0.5V 50 mA -20 mA +20 mA -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C 125 mV/ns
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5.5 4.5 5.5 IOZT IIN ICCT ICC IOLD IOHD Maximum I/O Leakage Current Maximum Input Leakage Current Maximum ICC/Input Max Quiescent Supply Current Minimum Dynamic Output Current (Note 3) 5.5 5.5 5.5 5.5 5.5 0.6 8.0 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.5 0.1 TA = -40C to+85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 5.0 1.0 1.5 80.0 75 -75 A A mA A mA mA V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VILor VIH V IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 A VIN = VILor VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC - 2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min
Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
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74ACT16543
AC Electrical Characteristics
VCC Symbol tPLH tPHL tPLH tPHL tPZH tPZL Parameter Propagation Delay Transparent Mode An to Bnor Bn to An Propagation Delay LEBAn, LEABn to An, Bn Output Enable Time OEBAn or OEABn to An or Bn CEBAn or CEABn to An or Bn tPHZ tPLZ Output Disable Time OEBAn or OEABn to An or Bn CEBAn or CEABn to An or Bn
Note 4: Voltage Range 5.0 is 5.0V 0.5V.
TA = +25C CL = 50 pF Min 3.8 3.5 4.7 Typ 5.9 5.5 6.9 6.3 6.3 7.3 Max 8.3 7.9 9.8 9.0 9.2 10.3
TA = -40C to +85C CL = 50 pF Min 3.0 2.6 3.4 3.1 3.0 3.6 Max 9.0 8.5 10.8 9.8 9.9 10.3 ns ns ns Units
(V) (Note 4) 5.0
5.0
3.9 4.2
5.0
4.9
2.8 5.0 2.6
5.2 5.0
8.0 7.6
2.1 2.0
8.3 8.1 ns
AC Operating Requirements
VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW An or Bn to LEBAn or LEABn Hold Time, HIGH or LOW An or Bn to LEBAn or LEABn Latch Enable, B to A Pulse Width, LOW
Note 5: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF
TA = -40C to +85C CL = 50 pF Units
(V) (Note 5) 5.0
Guaranteed Minimum 3.0 3.0 ns
5.0 5.0
1.5 4.0
1.5 4.0
ns ns
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation.Capacitance Typ 4.5 95.0 Units pF pF VCC = 5.0V VCC = 5.0V Conditions
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74ACT16543
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (SSOP), JEDEC MO-153, 6.1mm Wide Package Number MS56A
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74ACT16543 16-Bit Registered Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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